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may 2015 docid027815 rev 1 1 / 14 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. www.st.com STL4LN80K5 n - channel 800 v, 2.1 typ., 3 a mdmesh? k5 power mosfet in a powerflat? 5x6 vhv package datasheet - preliminary data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STL4LN80K5 800 v 2.6 3 a ? industrys lowest r ds(on) * area ? industrys best fom (figure of merit) ? ultra low - gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic reduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking package packing STL4LN80K5 4ln80k5 powerflat? 5x6 vhv tape and reel 5 6 7 8 1 2 3 4 t op v iew d(5, 6, 7, 8) g(4) s(1, 2, 3) 1 2 3 4 p o werfl a t? 5 x 6 vhv
contents STL4LN80K5 2 / 14 docid027815 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 3 test circuits ................................ ................................ ..................... 6 4 package information ................................ ................................ ....... 7 4.1 powerflat? 5x6 vhv package information ................................ ... 8 4.2 powerflat? 5x6 packing information ................................ ........... 11 5 revision hist ory ................................ ................................ ............ 13
STL4LN80K5 electrical ratings docid027815 rev 1 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t c = 25 c 3 a i d drain current (continuous) at t c = 100 c 1.9 a i dm (1) drain current (pulsed) 12 a p tot total dissipation at t c = 25 c 38 w dv/dt (2) peak diode recovery voltage slope 15 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 t j operating junction temperature - 55 to 150 c t stg storage temperature notes: (1) pulse width limited by safe operating area (2) i sd 3 a, dv/dt 100 a/s; v ds peak < v (br)dss (3) v ds 640 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 3.3 c/w r thj - pcb (1) thermal resistance junction - pcb 59 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2 oz cu table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by tjmax) tbd a e as single pulse avalanche energy (starting tj = 25 c, i d = i ar , v dd = 50 v) tbd mj
electrical characteristics STL4LN80K5 4 / 14 docid027815 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off - state symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 800 v i dss zero gate voltage drain current v gs = 0 v, v ds = 800 v 1 a v gs = 0 v, v ds = 800 v t c = 125 c 50 a i gss gate body leakage current v ds = 0 v, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 1.2 a 2.1 2.6 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 110 - pf c oss output capacitance - 9.5 - pf c rss reverse transfer capacitance - 0.4 - pf c oss(eq) (1) equivalent output capacitance v ds = 0 to 640 v, v gs = 0 v - tbd - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 18 - q g total gate charge v dd = 640 v, i d = 2 a v gs = 10 v, see figure 3: "gate charge test circuit" - 4 - nc q gs gate - source charge - tbd - nc q gd gate - drain charge - tbd - nc notes: (1) c oss eq is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 400 v, i d = 1.6 a, r g = 4.7 v gs = 10 v (see figure 2: "switching times test circuit for resistive load" and figure 7: "switching time waveform" ) - tbd - ns t r rise time - tbd - ns t d(off) turn - off delay time - tbd - ns t f fall time - tbd - ns
STL4LN80K5 electrical characteristics docid027815 rev 1 5 / 14 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 3 a i sdm (1) source - drain current (pulsed) - 12 a v sd (2) forward on voltage i sd = 3 a, v gs = 0 v - 1.6 v t rr reverse recovery time i sd = 3 a, di/dt = 100 a/s, v dd = 60 v, (see figure 4: "test circuit for inductive load switching and diode recovery times" ) - tbd ns q rr reverse recovery charge - tbd c i rrm reverse recovery current - tbd a t rr reverse recovery time i sd = 3 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c ( figure 4: "test circuit for inductive load switching and diode recovery times" ) - tbd ns q rr reverse recovery charge - tbd c i rrm reverse recovery current - tbd a notes: (1) pulse width limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5% table 9: gate source - zener diode symbol parameter test condition min. typ. max. unit. v (br)gs0 gate - source breakdown voltage i gs = 1ma, i d = 0 a 30 - - v the built - in back - to - back zener diodes have specifically been designed to enhance the device's esd capability. in this respect the zener voltage is appropriate to achieve an efficient and cost - effective intervention to protect the device's integrity. these integrated zener diodes thus avoid the usage of external components.
test circuits STL4LN80K5 6 / 14 docid027815 rev 1 3 test circuits figure 2 : switching times test circui t for resistive load figure 3 : gate charge test circuit figure 4 : test circuit for inductive load switching and diode recovery times figure 5 : unclamped inductive load test circuit figure 6 : unclamped inductive waveform figure 7 : switching time waveform
STL4LN80K5 package information docid027815 rev 1 7 / 14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at : www.st.com . ecopack ? is an st trademark.
package information STL4LN80K5 8 / 14 docid027815 rev 1 4.1 powerflat? 5x6 vhv package information figure 8 : powerflat? 5x6 vhv package outline bottom view side view t op view 1 2 3 4 pin 1 identification 8 7 6 5 8 7 6 5 1 2 3 4 pin 1 identification
STL4LN80K5 package information docid027815 rev 1 9 / 14 table 10: powerflat? 5x6 vhv package mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 5.95 6.15 6.35 d2 4.30 4.40 4.50 e2 2.40 2.50 2.60 e 1.27 l 0.50 0.55 0.60 k 2.60 2.70 2.80
package information STL4LN80K5 10 / 14 docid027815 rev 1 figure 9 : powerflat? 5x6 vhv recommended footprint (dimensions are in mm)
STL4LN80K5 package information docid027815 rev 1 11 / 14 4.2 powerflat? 5x6 packing information figure 10 : powerfla t? 5x6 tape (dimensions are in mm) figure 11 : powerflat? 5x6 package orientation in carrier tape
package information STL4LN80K5 12 / 14 docid027815 rev 1 figure 12 : powerflat? 5x6 reel
STL4LN80K5 revision history docid027815 rev 1 13 / 14 5 revision history table 11: document revision history date revision changes 29 - may - 2015 1 first release.
STL4LN80K5 14 / 14 doc id027815 rev 1 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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